With recent development of digital signal processing technologies, apparatus for recording and reproducing high-efficiency coded digital data of video signals etc., for example, digital video cassette tape-recorders (referred to hereinafter as DVC), have become popular.
A method for recording external input video signals such as composite signals, etc., with this recording and reproducing apparatus has been proposed in Japanese Patent Application Laid-Open Hei 7 No. 177469.
FIG. 8 shows one case of the above proposal. In FIG. 8, 101 designates an I/O block, 102 a VSP block, 103 a DRP block, 104 a control block, 105 an input video signal processing circuit, 106 a shuffling memory, 107 an orthogonal transformation circuit, 108 a framing circuit, 109 a PTG memory, 110 an encoder, 111 a decoder, 112 an ECC memory, 113 a deframing circuit, 114 an inverse orthogonal transformation circuit, 115 an output video signal processing circuit, 116 a synchronization separator circuit, 117 a synchronization detecting circuit, 118 a multiplexer, 119 a vertical and horizontal synchronization separator circuit, 120 an I/O control signal generator circuit, 121 an I/O PLL circuit, 122 a VSP control signal generator circuit, 123 a 2VSPPLL circuit, 124 a DRP control signal generator circuit, 125 a DRPPLL circuit, 126 a multiplexer, 127 a PBPLL circuit, 128 a reference synchronization generator and 129 a frame pulse generator circuit.
The recording and reproducing apparatus shown in FIG. 8 is comprised of I/O block 101 (input/output processor) as an input/output portion for handling input and output of video signals, VSP (Video Signal Processing) block 102 (compressing and expanding processor) for effecting predetermined processes on video data, a DRP (Data Recording Playback) block 103 (recording and reproducing processor) for performing recording and reproducing processes for recording and reproduction of video data and control block 104 for generating clock signals required for blocks 101 to 103 and performing the whole control of the apparatus.
Recording and reproduction of an externally input, composite signal, for example, using this recording and reproducing apparatus will be described hereinbelow.
To begin with, in control block 104, a synchronizing signal is extracted at synchronization separator circuit 116 from the input composite signal and the synchronizing signal is supplied to vertical and horizontal synchronization separator circuit 119 by way of multiplexer 118 when the synchronizing signal is detected by synchronization detecting circuit 117. Here, a synchronizing signal can be supplied to vertical and horizontal synchronization separator circuit 19 byway of multiplexer 118 even if no synchronization signal has been detected by synchronization detecting circuit 117 for a predetermined period of time.
In vertical and horizontal synchronization separator circuit 119, the synchronizing signal is separated into the vertical synchronizing signal and horizontal synchronizing signal. The phase of the horizontal synchronizing signal is drawn by I/OPLL circuit 121 to create a horizontal synchronizing signal of exact timing, which is supplied to I/O control signal generator circuit 120. This I/O control signal generator circuit 120 generates an I/O control signal whilst generating the 13.5 MHz clock signal which is recommended by the International Telecommunication Union (ITU-R) based on horizontal synchronization signal as a reference signal. These signals are supplied to I/O block 101.
The vertical synchronizing signal is obtained by frame pulse generator circuit 129 by detecting the frame length of video signal, and when the result falls within the range between ±1% of the standard frequency, frame pulses (to be referred to hereinbelow as the external input synchronizing signal) are generated based on the supplied vertical synchronizing signal. When the result falls equal to or greater than +1% or equal to or smaller than −1% of the standard vertical synchronizing signal, independent frame pulses (to be referred to hereinbelow as the internal free-running synchronizing signal) of +1% or −1% of the standard vertical synchronizing signal, respectively, are generated and supplied to 2VSPPLL circuit 123.
When the synchronizing signal is switched from the external input synchronizing signal to the internal free-running synchronizing signal, the counter for the internal running synchronizing signal is reset by the supplied vertical synchronizing signal, to thereby assure the continuity of the output frame pulses. On the other hand, for switching the synchronizing signal from the internal free-running synchronizing signal to the external input synchronizing signal, a window with a predetermined width is provided so that switching will be performed when the phase appears within the window, to thereby assure the continuity of the output frame pulses.
2VSPPLL circuit 123 draws the phase of the frame pulses so as to create frame pulses of exact timing, which are supplied to VSP control signal generator circuit 122. Provided from VSP control signal generator circuit 122 to VSP block 102 are a 18 MHz clock signal and a VSP control signal formed based on the 18 MHz clock signal.
DRPPLL circuit 125 draws the phase of the timing signal supplied from 2VSPPLL 123 so as to produce a 41.85 MHz clock signal set exactly in phase, which is supplied to DRP control signal generator circuit 124 by way of multiplexer 126. Supplied from DRP control signal generator circuit 124 to DRP block 103 are the 41.85 MHz clock signal and a DRP control signal produced based on the 41.85 MHz clock.
Next, in I/O block 101, the input composite signal is sampled and digitized by input video signal processing circuit 105 and further shaped into luminance data Y and chrominance data C. These signals are then written into shuffling memory 106 based on the 13.5 MHz clock signal supplied from control block 104.
In VSP block 102, based on the 18 MHz clock signal supplied from control block 104, the video data is read out from shuffling memory 106 and then the data is data compressed through orthogonal transformation circuit 107 and shaped into video data of one picture frame by framing circuit 108, which is added with the parity and then written into PTG memory 109.
In DRP block 103, the video data is read out from PTG memory 109 based on the 41.85 MHz clock signal supplied from control block 104 and is subjected to predetermined coding processes by encoder 110 and output to the recording head (not shown).
Next, the playback operation of this recording and reproducing apparatus will be described hereinbelow.
The video data is reproduced by a reproducing head (not shown) in the playback mode and supplied to decoder 111.
Here, in control block 104, the video data processed through the above decoder 111 (in DRP block 103) is supplied to PBPLL circuit 127, where a 41.8 gMHz clock signal is generated, which is supplied to DRP control signal generator circuit 124 via multiplexer 126. Supplied from DPR control signal generator circuit 124 to DRP block 103 are the 41.85 MHz clock signal and the DRP control signal. In DRP control signal generator circuit 124, the capstan speed is controlled based on the pilot signal recorded on the tape. That is, this allows the playback head to trace the recording track exactly, hence, it is possible to reproduce the video data correctly.
Reference synchronization generator 128 generates a synchronizing signal, which is supplied via multiplexer 118 to vertical and horizontal synchronization separator circuit 119. The phase of the vertical synchronizing signal separated by vertical and horizontal synchronization separator circuit 119 is drawn by 2VSPPLL circuit 123 by way of frame pulse generator circuit 129 so as to allow VSP control signal generator circuit 122 to generate a 18 MHz clock signal and a VSP control signal, which are supplied to VSP block 102.
Also, the phase of the horizontal synchronizing signal separated by vertical and horizontal synchronization separator circuit 119 is drawn by I/OPLL circuit 121 so as to allow I/O control signal generator circuit 120 to generate a 13.5 MHz clock signal and I/O control signal, which are supplied to I/O block 101.
In DRP block 103, the reproduced data is supplied to decoder 111 as above, where the data is subjected to the predetermined decoding process, and the decoded data is written into ECC memory 112 based on the 41.85 MHz clock signal supplied from control block 104 whilst being error-corrected.
In VSP block 102, the data is read out from ECC memory 112 based on the 18 MHz clock signal supplied from control block 104, and is supplied via deframing circuit 113 to inverse orthogonal transformation circuit 114, where the data is subjected to inverse orthogonal transformation based on the VSP control signal, and is written based on the 18 MHz clock signal into shuffling memory 106 so that one frame of video data is formed.
In I/O block 101, the video data is readout from shuffling memory 106 based on the 13.5 MHz clock signal supplied from control block 104 and is transformed into the composite data through output video signal processing circuit 115 based on the I/O control signal whilst being converted into analog form and is output externally.
In this way, the video data can be recorded in accordance with the external input synchronizing signal when the vertical synchronizing signal of the external input video data during recording falls within the range between ±1% of the standard frequency and can be recorded in accordance with the 1% incremented or decremented internal free-running synchronizing signal when the synchronizing signal falls equal to or greater than +1% or equal to or smaller than −1% of the standard frequency. Further, since upon switching from the external input synchronizing signal to the internal free-running synchronizing signal or vice versa, switching between the output vertical synchronizing signals can be performed keeping continuity, it is possible to make an accurate drum servo control on the rotational rate of the recording head.
Also in reproducing, the video data recorded on the tape can be correctly reproduced.
Nevertheless, since writing to and reading from the shuffling memory are asynchronous, if data reading starts before the completion of writing of one frame of data, the data before being overwritten, i.e., of the previous old frame will mix in the readout data. Further, if writing of the next frame of data starts before the completion of reading of one frame of data, the data after being overwritten, i.e., of the new frame will mix in the readout data. These phenomena are considered to occur frequently especially when the length of the vertical synchronizing signal constantly falls out of the range between ±1% of the standard signal. However, Japanese Patent Application Laid-Open Hei 7 No. 177469 has no reference to this problem.
Moreover, there is a possibility that video data of an external input might be recorded with a lack of order in some cases depending upon the types of input sources. Examples include discontinuity between fields when tape of scenes taken with breaks is reproduced and input, discontinuity between fields due to channel change during input from a tuner, increase or decrease in the number of lines in one frame, mixture of different types of frame data, continuous input of unpaired fields in non-interlaced signal input such as from a game machine etc., synchronous failures due to blank signal input and phase discontinuity of the synchronizing signal after recovery.